Scaling of FinFET devices to dimensions relevant to and exceeding ground rule requirements for a 22 nm node requires the formation of one or more silicon (Si) fins on the order of 10-20 nm thick. A FinFET device is a nonplanar, double-gate transistor built on an SOI (silicon-on-insulator) substrate. The definition of this fin can be performed directly using a lithographic technique or an indirect patterning technique such as the sidewall image transfer (SIT) process. Regardless of the method, it is anticipated that control of the final fin width will be a significant issue in the manufacturing of FinFETs. Single nanometer variation in this parameter results in a ˜7% change in the effective body thickness of the channel. As a consequence variability in the threshold voltage, Vt, of the device across the wafer is expected to be a concern.
For a 15 nm thick fin, a single nanometer variation results in a ˜7% change in the effective body thickness of the channel. As a consequence, variability in the threshold voltage, Vt, of the device across the wafer is expected to be a concern. Control gates for other thin-body devices have been shown to be an effective way of electrically modulating Vt after completing device fabrication. However, due to the unique structure of a FinFET, integration of a control gate is problematic without compromising the integration density or electrical integrity of the device structure.
Therefore, there is a need for a solution to the FinFET shortcomings as described above.